1. Field of the Invention
The present invention relates to optimization of integrated circuit hierarchical design and, more particularly, an integrated circuit hierarchical design system and an integrated circuit hierarchical design program which eliminate the need of distribution of propagation delays on a path between flip-flops connecting layers.
2. Description of the Related Art
When composing a large-scale integrated circuit including layer blocks, optimization is conducted while maintaining a layered structure. In the optimization, delays of a signal propagating between flip-flops which determine an operating frequency of the integrated circuit is analyzed.
In this case, because designing is made for each layer, with a signal propagating over a plurality of layers, its signal propagation delays should be divided for each layer, which requires calculation of propagation delays whose precision is hard to be obtained and whose execution relies on prediction.
Examples of methods for solving such a problem are recited, for example, in Japanese Patent Laying-Open (Kokai) No. 05-258006 (Literature 1), Japanese Patent Laying-Open (Kokai) No. 06-76012 (Literature 2), Japanese Patent Laying-Open (Kokai) No. 2000-83002 (Literature 3) and “Itaru Sakurai: Basis of Digital Design by HDL, pp. 128-129, FIGS. 5-18, Techno-press” (Literature 4).
The method disclosed in Literature 1 distributes delays of a signal propagating between layers, with timing between layers defined by a time storage means. According to the method of Literature 1, design is made after setting time when a signal passes between the respective layers. More specifically, by defining timing of a higher layer at a time point when a lower layer is designed, a problem derived from a lack of coincidence in timing with the design of the lower layer made at an early stage of the designing will be solved at a time of designing the higher layer which is made at a later stage of the designing.
The method recited in Literature 2 distributes delays of a signal propagating between layers by using hierarchical development reference data.
On the other hand, the method recited in Literature 3 changes a layered structure by extracting a flip-flop and making a section by a layer changing unit to have an input of the flip-flop reside in the vicinity of the section of a layer such that with respect to a signal propagating between the layers, there exists no path that fails to pass through the flip-flop.
According to the method in Literature 3, in a case of a path leading to an output terminal from an input terminal without passing through a flip-flop, optimization processing can be executed without requiring special processing such as hierarchy destruction and constraint value regeneration.
FIG. 9 shows an example of optimization disclosed in the method of Literature 3.
Literature 4 points out that because out of signals propagating between flip-flops which determine an operating frequency of the integrated circuit, with respect to a signal propagating over the layers whose signal propagation delay value is hard to be minimized, in particular, signal propagation between flip-flops is hierarchically designed, signal propagation from an output flip-flop to a layer exit, from the layer exit to a layer entrance and from the layer entrance to an input flip-flop should be divisionally handled.
Furthermore, Literature 4 recommends a design rule that a register formed of a flip-flop should be placed at an input/output of a block without fail in order to improve external estimation precision.
The above-described conventional techniques all have the following shortcomings.
The method disclosed in Literature 1 distributes delays of a signal propagating between layers, with timing between layers defined by a time storage means. The method in Literature 1 therefore fails to solve the problem that with respect to a signal propagating between divided layers, signal propagation delays need to be divided into the plural.
In addition, the method in Literature 1 aims at solving a problem derived from design of a lower layer at a time when a higher layer is designed after finishing designing of the lower layer and not at solving the problem that signal propagation delays need to be divided into the plural.
Similarly, neither aims the method of Literature 2 at eliminating the need of dividing signal propagation delays into the plural.
On the other hand, by changing a layered structure by making a section, the method disclosed in Literature 3 enables optimization processing to be executed without special processing such as hierarchy destruction which changes a layered structure and constraint value regeneration when there exists a path leading to an output terminal from an input terminal without passing through a flip-flop.
The method in Literature 3 which changes a layered structure aims at avoiding a signal propagating between flip-flops that passes through a layer and fails to eliminate the need of dividing signal propagation delays into the plural because even after changing the layered structure, there remains at least a path leading from a flip-flop to a layer exit and a path leading from the layer exit to a layer entrance as shown in FIG. 9 to inevitably require distribution of delays on these two paths.
The literature 4 recommends a design rule that a register formed of a flip-flop should be placed at an input/output of a block without fail in order to improve external estimation precision, while it discloses no specific method therefor to fail to eliminate the need of dividing signal propagation delays into the plural.